1. Field of the Invention
The present invention generally relates to a storage area network (“SAN”) employing a plurality of Fibre Channel switches which are connected together to form a fabric. The present invention specifically relates to a storage area network link integrity tester.
2. Description of the Related Art
FIG. 1 illustrates a SAN 110 employing one or more fibre channel switches 20 and a plurality of end devices 30. As known in the art, fibre channel switches 20 are used to establish a fibre channel communication network topology (i.e., fabric) providing direct connections between end devices 30 (e.g., personal computers, workstations, servers and the like). Testing of the fibre channel communication network topology often requires the use of a large quantity of expensive equipment, particularly a large quantity of additional fibre channel switches 20 and end devices 30 for testing purposes.
With known SANs, higher data rates and embedded clocks can often result in greater susceptibility to link issues within the SAN. Link issues can include jitter and degrading bit error rate (BER) performance. Data Patterns that may produce jitter problems can be found discussed in the document T11.2/Project/230/Rev10 entitled Fibre Channel—Methodologies for Jitter Specification. The process to determine whether jitter, signal integrity, or degrading bit error rates exist is very complex and can require a great deal of expertise in the area of electronics and signal analysis. Jitter is an unwanted variation of one or more signal characteristics in electronics and telecommunications. Jitter may be seen in characteristics such as the interval between successive pulses, or the amplitude, frequency, or phase of successive cycles.